Engineers Stack Silicon in 3D, a Breakthrough That Could Keep Moore's Law Alive for Years

As the decades-long march of shrinking transistors runs up against the laws of physics, researchers have found another way to pack more computing power into the same space: stacking silicon circuits in multiple layers, one directly atop another.

A team led by Qing Cao, a materials science and engineering professor at the University of Illinois Urbana-Champaign's Grainger College of Engineering, has demonstrated a method for building true three-dimensional silicon chips — a long-sought goal that could extend Moore's Law, the principle that computing power roughly doubles every couple of years, well into the future. The work was published in the journal Nature.

The central obstacle to 3D chips has been heat. Conventional silicon transistors are fabricated at very high temperatures, which would damage the delicate circuitry on layers beneath them. Cao's team sidestepped the problem using ultra-thin silicon membranes and a low-temperature manufacturing process, allowing additional layers to be added without destroying what lay below.

A key innovation was the use of "junctionless" transistors, which can be prepared before the stacking process even begins. Using that approach, the researchers built three stacked silicon layers, each containing 625 transistors, and reported manufacturing yields between 98% and 100% — a remarkably high success rate for such an intricate process. Crucially, the stacked devices delivered performance comparable to standard silicon transistors made at much higher temperatures.

The payoff could be substantial. Stacking circuits vertically rather than spreading them across a flat surface allows chipmakers to dramatically increase computing density, shorten the distances signals must travel, and reduce energy consumption — gains that matter enormously for power-hungry artificial intelligence systems and data centers.

For more than half a century, the semiconductor industry has sustained its breakneck progress by making transistors ever smaller. But individual components are now measured in mere atoms, and further miniaturization is bumping against fundamental limits. Researchers and companies have increasingly turned to "monolithic 3D integration" as the next frontier. Cao's demonstration suggests the approach can work at high yield with materials the industry already knows how to handle, an important consideration for any technology hoping to move from the laboratory to commercial fabrication plants. Significant engineering challenges remain before stacked silicon reaches consumer devices, but the result marks one of the most concrete steps yet toward chips that grow up instead of out.