NASA's New Radiation-Hardened RISC-V Space Chip Runs 500 Times Faster Than Current Deep-Space Processors

PASADENA, Calif. — A radiation-hardened computer chip being tested at NASA's Jet Propulsion Laboratory is running roughly 500 times faster than the processors currently flying aboard the agency's deepest-space missions, far exceeding its design specification and putting the chip on track for certification on lunar and Mars-bound spacecraft, NASA officials said this week.

The processor, formally known as the High-Performance Spaceflight Computing chip, or HPSC, was developed jointly by JPL and Microchip Technology Inc. of Chandler, Ariz., under a $50 million Space Technology Mission Directorate contract that began in 2021. JPL engineers said the device passed initial bench testing in February and has since survived a battery of total-ionizing-dose, single-event-effect and thermal-cycling tests at the lab's environmental test facility in Pasadena. "It is performing as intended, and in some benchmarks it is exceeding what we thought was possible at this radiation tolerance," said Wesley Powell, JPL's principal technologist for avionics. The design target was a 100-fold improvement over the chips currently in use; benchmarks show the HPSC running at roughly 500 times the throughput of the BAE Systems RAD750, the workhorse spaceflight processor that powers spacecraft from the Mars Perseverance rover to the James Webb Space Telescope.

The chip is the first NASA flight processor built around the open-source RISC-V instruction set architecture and uses an eight-core configuration that can be reconfigured in flight to trade raw performance for radiation tolerance, depending on the radiation environment a spacecraft is passing through. Microchip is fabricating the parts on Samsung's 12-nanometer process — a substantial leap from the 250-nanometer node used for the RAD750 — and adds hardware-level error-correction and triple-redundancy logic to harden the design against galactic-cosmic-ray and solar-particle hits.

The added compute power is meant to enable a generation of spacecraft that can make decisions without waiting for instructions from Earth. "We want a Mars helicopter that can replan its own flight path when it sees a dust storm, a lunar rover that can navigate a crater rim by itself, an orbiter that can decide which of its own images are interesting enough to send home," said Lori Glaze, NASA's associate administrator for the Science Mission Directorate. Round-trip light time to Mars can exceed 40 minutes, making most autonomous decisions on the ground impractical.

The chip must complete its full qualification campaign — including high-energy proton testing at the Texas A&M cyclotron facility this summer and a destructive single-event-latchup test in the fall — by late 2026 to remain eligible for NASA's Artemis program, which is targeting a crewed lunar landing in early 2028. JPL said the first HPSC parts could fly on Earth-orbiting science demonstrators as soon as 2027, with the first deep-space deployment expected on the agency's planned Mars Sample Return mission and on the Artemis V lunar rover.

The leap in computing power is among the largest single jumps in NASA's flight-computer history. The RAD750, the current standard, was first qualified in 2001 and runs at roughly 200 megahertz; the HPSC's eight cores together deliver more than 1.2 trillion operations per second. "This is the difference between giving a spacecraft a 1990s desktop and giving it a modern laptop," Powell said. "For deep space, that changes what we can ask a robot to do on its own."